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| this is information on a product in full production. august 2013 docid022344 rev 4 1/79 stm8tl52g4 STM8TL52F4 stm8tl53c4 stm8tl53g4 stm8tl53f4 8-bit ultralow power touch sensing microcontroller with 16 kbytes flash, proxsense?, timers, usart, spi, i2c datasheet - production data features ? operating conditions ? operating power supply: 1.65 v to 3.6 v ? temperature range: ?40 c to 85 c ? low power features ? 4 low power modes: wait, active-halt with awu (1 a), active-halt with proxsense? (10 a with scan every 200 ms), halt (0.4 a) ? dynamic power consumption: 150 a/mhz ? fast wakeup from halt mode: 4.7 s ? ultralow leakage per i/o: 50 na ? advanced stm8 core ? harvard architecture with 3-stage pipeline ? max freq.16 mhz,16 cisc mips peak ? memories ? up to 16 kbytes of flash program including up to 2 kbytes of data eeprom ? error correction code (ecc) ? flexible write and read protection modes ? in-application and in -circuit programming ? data eeprom capability ? 4 kbytes of static ram ? clock management ? internal 16 mhz factory-trimmed rc ? internal 38 khz low consumption rc driving both the iwdg and the awu ? reset and supply management ? ultralow power, ultrasafe power-on reset/ power-down reset ? interrupt management ? nested interrupt controller with software priority control ? up to 22 external interrupt sources ? i/os ? up to 23 with 22 mappable on external interrupt vectors ? i/os with programmable input pull-ups, high sink/source capability ? proxsense? patented acquisition technology with up to 300 touch sensing channels (20 receiver/transmitter channels and 15 transmitter channels) supporting projected capacitive acquisition method suitable for proximity detection. ? timers ? two 16-bit general purpose timers (tim2 and tim3) with up and down counter and 2 channels (used as ic, oc, pwm) ? one 8-bit timer (tim4) with 7-bit prescaler ? independent watchdog ? window watchdog ? auto-wakeup unit ? beeper timer with 1, 2 or 4 khz frequencies ? communication interfaces ? spi synchronous serial interface ?fast i 2 c multimaster/slave 400 khz ? usart with fractional baud rate generator ? development support ? hardware single wire interface module (swim) for fast on-chip programming and non intrusive debugging ? in-circuit emulation (ice) 5 & 1 & 0 . x m m 5 & 1 & 0 . x m m 4 3 3 / 0 www.st.com
contents stm8tl5xxx 2/79 docid022344 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 single wire data interface (swim) and debug module . . . . . . . . . . . . . . . 12 3.4 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7.1 dual-mode voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7.2 proxsense voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9 system configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.12 auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.13 general purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.14 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.15 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.16 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.17 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.18 proxsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.19 touchsensing dedicated libra ry available upon request . . . . . . . . . . . . . 16 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 docid022344 rev 4 3/79 stm8tl5xxx contents 4 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.3 power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 44 9.3.4 proxsense regulator voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.6 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.7 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3.9 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.1 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.1.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.1.2 stm-studio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.1.3 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.2 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 contents stm8tl5xxx 4/79 docid022344 rev 4 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 docid022344 rev 4 5/79 stm8tl5xxx list of tables 5 list of tables table 1. device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. legends/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3. stm8tl5xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. unique id registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 11. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 14. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. proxsense voltage regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 17. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19. total current consumption in halt mode and active-halt mode v dd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21. proxsense peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. hsi_pxs oscillator charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 25. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. program memory endurance & rete ntion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. data memory endurance & retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 30. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 31. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 32. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 33. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 34. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 35. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 36. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 37. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 38. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 39. ufqfpn48 - 48-lead ultra thin fine pitch quad flat no-lead package (7x7), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 40. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package (4x4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 41. tssop20 - 20-pin thin shrink small outline pack age mechanical data . . . . . . . . . . . . . . . 73 table 42. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 list of figures stm8tl5xxx 6/79 docid022344 rev 4 list of figures figure 1. stm8tl5xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. stm8tl53 48-pin ufqfpn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. stm8tl53g4u6 28-pin ufqfpn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. stm8tl52g4u6 28-pin ufqfpn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. stm8tl53f4p6 tssop20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. STM8TL52F4p6 tssop20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 11. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12. i dd(run) vs. v dd , f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 13. i dd(wait) vs. v dd. f cpu = 16 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14. typ. i dd(halt) vs. v dd. f cpu = 2 mhz and 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 15. typical hsi frequency vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 16. typical hsi accuracy vs. temperature, vdd = 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 17. typical lsi frequency vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 18. typical pull-up resistance r pu vs. v dd with v in =v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 19. typical v il and v ih vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 20. typ. v ol at v dd = 1.8 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 21. typ. v ol at v dd = 3.0 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 22. typ. v dd - v oh at v dd = 1.8 v(standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 23. typ. v dd - v oh at v dd = 3.0 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 24. typ. v dd - v oh at v dd = 1.8 v (proxsense_tx ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 25. typ. v dd - v oh at v dd = 1.8v (proxsense rx ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 26. typical nrst pull-up resistance r pu vs. v dd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 27. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 28. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 29. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 30. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 31. typical application with i 2 c bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 32. ufqfpn48 - 48-lead ultra thin fine pitch quad flat no-lead package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 33. ufqfpn48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 34. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 35. ufqfpn28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 36. tssop20 - 20-pin thin shrink small outline package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 37. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 figure 38. stm8tl5xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 docid022344 rev 4 7/79 stm8tl5xxx introduction 25 1 introduction this datasheet provides the stm8tl52g4 , STM8TL52F4, stm8tl53c4, stm8tl53g4 and stm8tl53f4 pinouts, ordering information, mechanical and electrical device characteristics. for complete information on the microcontroller memory, registers and peripherals, please refer to the stm8tl5xxx reference manual (rm0312) and to the stm8tl5xxx flash programming manual (pm0212) for flash memory related information. for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module us er manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). all devices of the stm8tl5xxx produc t line provide the following benefits: ? advanced capacitive sensing ? patented proxsense ? acquisition peripheral, providing high-end acquisition, filtering and environment adaptation ? outstanding signal-to-noise ratio for touch and proximity sensing ? up to 300 projected capacitive channels ? reduced system cost ? up to 16 kbytes of low-density embedded flash program memory including up to 2 kbytes of data eeprom ? high system integration level with internal clock oscillators and watchdogs ? smaller battery and cheaper power supplies ? low power consumption and advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? less than 150 a/mhz, 0.8 a in active-halt mode with awu, and 0.3 a in halt mode ? clock gated system and optimized power management ? short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals ? full documentation and a wide choice of development tools ? product longevity ? advanced core and peripherals made in a state-of-the-art technology ? product family operating from 1.65 v to 3.6 v supply note: proxsense ? is a trademark of azoteq (pty) ltd. description stm8tl5xxx 8/79 docid022344 rev 4 2 description the stm8tl5xxx devices feature the enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. it us es a proxsense charge transfer capacitive acquisition method that is capable of near range proximity detection. the family includes an integrated debug modu le with a hardware in terface (swim) which allows non-intrusive in-application debugging and ultrafast flash programming. all stm8tl5xxx microcontrollers feature low po wer low-voltage single-supply program flash memory. the stm8tl5xxx are based on a generic set of state-of-the-art peripherals. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families including 32-bit families. this ma kes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. docid022344 rev 4 9/79 stm8tl5xxx description 25 table 1. device features features STM8TL52F4 stm8tl53f4 stm8tl52g4 stm8tl53g4 stm8tl53c4 flash (kbytes) 16 data eeprom (kbytes) 2 ram (kbytes) 4 timers basic 1 (8-bit) general purpose 2 (16-bit) communi cation interfaces spi 1 i2c 1 usart 1 gpios 12 17 23 proxsense up to 12 touch sensing channels (5 receiver/ transmitter channels and 2 transmitter channels) up to 30 touch sensing channels (5 receiver/ transmitter channels and 6 transmitter channels) up to 25 touch sensing channels (8 receiver/ transmitter channels and 2 transmitter channels) up to 72 touch sensing channels (8 receiver/ transmitter channels and 9 transmitter channels) up to 300 touch sensing channels (20 receiver/ transmitter channels and 15 transmitter channels) others window watchdog, independent watchdog, two 16-mhz and one 38-khz internal rc, auto- wakeup counter, beeper cpu frequency 16 mhz operating voltage 1.65 to 3.6 v operating temperature -40 to +85 c packages tssop20 ufqfpn28 ufqfpn48 product overview stm8tl5xxx 10/79 docid022344 rev 4 3 product overview figure 1. stm8tl5xxx block diagram legend: awu: auto-wakeup unit int. rc: internal rc oscillator i2c: inter-integrated circuit multimaster interface por/pdr: power on reset / power down reset spi: serial peripheral interface swim: single wire interface module usart: universal synchronous / as ynchronous receiver / transmitter iwdg: independent watchdog wwdg: window watchdog proxsense?: capacitive sensing peripheral ms19122v3 address, control and data bases 16 mhz internal rc 38 khz internal rc clock controller and css 16 kbytes program memory iwdg (38 khz clock) clocks to core and peripherals power supply supervisor por/pdr v dd18 pdr debug module (swim) i2c spi usart 16-bit timer 2 wwdg beeper 4 kbytes ram port a port b port d 16-bit timer 3 8-bit timer 4 awu (38 khz clock) pxs_rx(0a..9a, 0b..9b) pxs_tx(0..14) pxs_rfin pxs_trig pxs_vreg v dd = 1.65 v to 3.6 v v ss nrst scl, sda mosi, miso, sck, nss rx, tx, ck beep pa[7:0] pb[6:0] pd[7:0] stm8 core nested interrupt controller up to 22 external interrupts proxsense voltage reg. 16 mhz dedicated internal rc voltage reg. @ v dd $ a t a % 0 2 / - + b y t e s docid022344 rev 4 11/79 stm8tl5xxx product overview 25 3.1 central proc essing unit stm8 the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect an d relative addressing, and 80 instructions. architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching most instructions ? x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify - write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16 mbytes linear memory space ? 16-bit stack pointer - access to a 64 kbytes level stack ? 8-bit condition code register - 7 condition fl ags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for lookup tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumu lator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers product overview stm8tl5xxx 12/79 docid022344 rev 4 3.2 development tools development tools for the stm8 microcontrollers include: ? the st-link very low-cost professional tool to debug and program ? the stvd high-level language debugger including c compiler, assembler and integrated development environment ? the stvp flash programming software ? the stm-studio real-time and non-intrusive graphical interface used to probe application variables and data the stm8 also comes with starter kits, ev aluation boards and low-cost in-circuit debugging/programming tools. 3.3 single wire data interface (swim) and debug module the debug module with its single wire data inte rface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be acti vated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, also cpu operation can be monitored in real- time by means of shadow registers. 3.4 interrupt controller the stm8tl5xxx features a nested vectored interrupt controller: ? nested interrupts with 3 software priority levels ? 22 interrupt vectors with hardware priority ? up to 22 external interrupt sources on 10 vectors ? trap and reset interrupts 3.5 memory the stm8tl5xxx devices have t he following main features: ? 4 kbytes of ram ? the eeprom is divided into two memory arrays (see the stm8tl5xxx reference manual (rm0312) for details on the memory mapping): ? 16 kbytes of low-density embedded flash program including up to 2 kbytes of data eeprom. data eeprom and flash pr ogram areas can be write protected independently by using the memory access security mechanism (mass). ? 64 option bytes (one block) of which 5 bytes are already used for the device. ? error correction code is implemented on the eeprom. docid022344 rev 4 13/79 stm8tl5xxx product overview 25 3.6 low power modes to minimize power consumption, the prod uct features three mcu low power modes: ? wait mode: cpu clock stopped, select ed peripherals at full clock speed. ? active-halt mode: ? when wakeup time is programmed in the awu unit, the cpu and peripheral clocks are stopped. the ram content is preserved. ? when a proxsense acquisition is ongoing , the wakeup is on proxsense interrupts; the cpu and the other periph eral clocks are stopped. ? halt mode: cpu and peripheral clocks are stopped, the device remains powered on. wakeup is triggered by an external interrupt. the proxsense peripheral can return to low power mode between each conversion. the proxsense acquisition can be operated in run, wait and active-halt modes. 3.7 voltage regulators the stm8tl5xxx devices embed an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals and a second internal voltage regulator providing a stable power supply (around 1.45v) for the proxsense peripheral. 3.7.1 dual-mode voltage regulator this regulator has two different modes: main voltage regulator mode (mvr) and low power voltage regulator mode (lpvr). when in active-halt mode, the regulator remains in mvr if proxsense is active. when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in or der to reduce current consumption unless proxsense is enabled. 3.7.2 proxsense voltage regulator this regulator provides a very stable voltage to power the proxsense peripheral including proxsense pins in order to be independent of any power supply variations. this regulator is switched on while the proxsense periphe ral is enabled (bit pxsen = 1) and bit low_power is set to ?0? in register pxs_cr1. otherwise, when low_power is set to ?1?, this regulator is only enabled during conversions (while cipf = 1 and syncpf = 0). 3.8 clock control the stm8tl5xxx embeds a robust clock controller. it is used to distribute the system clock (sysclk) to the core and the peripherals and to manage clock gating for low power modes. this system clock is a 16-mhz high speed in ternal rc oscillator (hsi rc), followed by a programmable prescaler. in addition, a 38 khz low speed internal rc o scillator is used by t he independent watchdog (iwdg) and auto-wakeup unit (awu). product overview stm8tl5xxx 14/79 docid022344 rev 4 3.9 system config uration controller the system configuration cont roller provides the capabilit y to remap some alternate functions on different i/o ports. tim3 channels can be remapped. 3.10 independent watchdog the independent watchdog (iwdg) peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 38 khz lsi internal rc clo ck source, and thus stays active even in case of a cpu clock failure. 3.11 window watchdog the window watchdog (wwdg) is based on a 7-bi t downcounter that can be set as free- running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.12 auto-wakeup counter the auto-wakeup (awu) counter is used to wakeup the device from active-halt mode. 3.13 general purpos e and basic timers stm8tl5xxx devices contain two 16-bit gene ral purpose timers (tim2 and tim3) and one 8-bit basic timer (tim4). 16-bit general purpose timers the 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. they perform a wide range of functions, including: ? timebase generation ? measuring the pulse lengths of input signals (input capture) ? generating output waveforms (output compare, pwm and one pulse mode) ? interrupt capability on various events (capt ure, compare, overfl ow, break, trigger) ? synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase gene ration with interrupt generation on timer overflow. docid022344 rev 4 15/79 stm8tl5xxx product overview 25 3.14 beeper stm8tl5xxx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 khz when the lsi clock is operating at a frequency of 38 khz. 3.15 usart the usart interface (usart) allows full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. ? 1 mbit/s full duplex sci ? spi emulation ? high precision baud rate generator ? single wire half duplex mode 3.16 spi the serial peripheral interface (spi) provides half/ full duplex synchronous serial communication with external devices. ? maximum speed: 8 mbit /s (fsysclk/2) both fo r master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on 2 lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? hardware crc calculation ? slave/master selection input pin 3.17 i 2 c the i 2 c bus interface (i 2 c) provides multi-master ca pability, and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. ? master, slave and mult i-master capability ? dual addressing mode capability ? standard mode up to 100 khz and fast speed modes up to 400 khz ? 7-bit and 10-bit addressing modes ? hardware crc calculation product overview stm8tl5xxx 16/79 docid022344 rev 4 3.18 proxsense the proxsense peripheral uses a charge-transfer method to detect capacitance changes. ? up to 300 capacitive sensing channels composed of 15 transmitters and 20 receivers with up to 10 rx channe ls acquired in parallel ? fast acquisition with a typical scan time of 250 s for 10 rx channels ? configurable internal sampling capacitor (c s ) ? electrode parasitic capacitance compensation (epcc) to ensure the best sensitivity in all user environments ? rf noise detection, allowing to reject corrupted samples ? external trigger to de-synchronize the acquisition from known noise ? can be configured to return to low power mode between each conversion ? acquisition possible in run, wait and active-halt modes 3.19 touchsensing de dicated library available upon request ? complete c source code library with firmware examples (misra compliant) ? multifunction capability to co mbine capacitive sensing fu nctions with traditional mcu features ? compatible with proximity, touchkey, linear and rotary touch sensor implementation ? configuration of all proxsense parameters ? extra filtering and calibration functions ? touchsensing user interface through firmware api for status reporting and application configuration ? compliance with cosmic, iar and raisonance c compilers docid022344 rev 4 17/79 stm8tl5xxx pin description 25 4 pin description figure 2. stm8tl53 48-pin ufqfpn package pinout 1. hs corresponds to 20 ma hi gh sink/source capability. 2. power supply pins must be correctly decoupled with capacitors near the pins. please refer to the power supply circuitry details in section 9.3.2: power supply on page 44 and the stm8tl5xxx reference manual (rm0312), section 6: power supply. - 3 6 5 & 1 & 0 . 0 8 3 ? 4 8 ( 3 0 " " % % 0 3 7 ) - ( 3 0 ! ; 4 ) - ? # ( = 3 0 ) ? . 3 3 ( 3 0 ! ; 4 ) - ? # ( = 5 3 ! 2 4 ? # + 3 0 ) ? 3 # + ( 3 0 ! ) # ? 3 $ ! 5 3 ! 2 4 ? 4 8 3 0 ) ? - ) 3 / ( 3 0 ! ) # ? 3 # , 5 3 ! 2 4 ? 2 8 3 0 ) ? - / 3 ) ( 3 0 ! 6 $ $ 6 3 3 . 2 3 4 ( 3 0 ! # , + ? # # / 0 8 3 ? 4 2 ) ' ( 3 0 ! 0 8 3 ? 2 & ) . ( 3 0 ! 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 " ( 3 0 8 3 ? 4 8 0 " ( 3 0 8 3 ? 4 8 0 " ( 3 0 8 3 ? 4 8 0 " ( 3 0 8 3 ? 4 8 0 " ( 3 0 8 3 ? 4 8 4 ) - ? 4 2 ) ' 0 " ( 3 0 8 3 ? 4 8 4 ) - ? 4 2 ) ' 0 $ ( 3 0 8 3 ? 4 8 4 ) - ? # ( 0 $ ( 3 0 8 3 ? 4 8 4 ) - ? # ( 0 $ ( 3 0 8 3 ? 4 8 4 ) - ? # ( 0 $ ( 3 0 8 3 ? 4 8 4 ) - ? # ( 6 $ $ ) / 6 3 3 ) / 0 $ ( 3 0 8 3 ? 4 8 0 $ ( 3 0 8 3 ? 4 8 0 $ ( 3 0 8 3 ? 4 8 0 $ ( 3 0 8 3 ? 4 8 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 2 8 b 0 8 3 ? 2 8 a 0 8 3 ? 6 2 % ' pin description stm8tl5xxx 18/79 docid022344 rev 4 figure 3. stm8tl53g4u6 28-pin ufqfpn package pinout 1. hs corresponds to 20 ma hi gh sink/source capability. 2. power supply pins must be correctly decoupled with capacitors near the pins. please refer to the power supply circuitry details in section 9.3.2: power supply on page 44 and the stm8tl5xxx reference manual (rm0312), section 6: power supply. ; 4 ) - ? # ( ] 5 3 24 3 0) 3 ( 3 0 5 1 0 . ) 35324 4830) -)3/ ( 3 0 ) 3 , 5 3 2428 3 0)- /3 ) ( 3 0 0 83 6 2 .2 3 4 ( 3 0 0 ( 3 3 0). 33 4)- ( ] 0 (3 3 7)- 0 0 (3 083484)-42) 0( 3 08 3 48 4)- ( 0 (3 083484)-( 0 (3 083484)-( 0 (3 083484)-( 0 ( 3 08 3 48 0 (3 08348 0 (3 08348 0 ( 3 08 3 48 0 8 3 28 a 0 8 3 28 a 0 8 3 28 a , / 08 3 42) ( 3 0 0 8 3 2). ( 3 0 0 8 3 28 a 083 28a 0 8328 a 0 8 3 28 a 0 8 3 28 a m s 1 9 1 00 v 1 6 3 3 6 $ $ docid022344 rev 4 19/79 stm8tl5xxx pin description 25 figure 4. stm8tl52g4u6 28-pin ufqfpn package pinout 1. hs corresponds to 20 ma hi gh sink/source capability. 2. power supply pins must be correctly decoupled with capacitors near the pins. please refer to the power supply circuitry details in section 9.3.2: power supply on page 44 and the stm8tl5xxx reference manual (rm0312) section 6: power supply. ; 4 ) - ? # ( ] 5 3 ! 2 4 ? # + 3 0 ) ? 3 # + ( 3 0 ! 5 & 1 & 0 . ) # ? 3 $ ! 5 3 ! 2 4 ? 4 8 3 0 ) ? - ) 3 / ( 3 0 ! ) # ? 3 # , 5 3 ! 2 4 ? 2 8 3 0 ) ? - / 3 ) ( 3 0 ! 0 8 3 ? 6 2 % ' . 2 3 4 ( 3 0 ! 0 ! ( 3 3 0 ) ? . 3 3 ; 4 ) - ? # ( ] 0 ! ( 3 3 7 ) - " % % 0 0 " ( 3 4 ) - ? 4 2 ) ' 0 $ ( 3 4 ) - ? # ( 0 $ ( 3 4 ) - ? # ( 0 $ ( 3 4 ) - ? # ( 0 $ ( 3 4 ) - ? # ( 0 $ ( 3 0 $ ( 3 0 $ ( 3 0 8 3 ? 4 8 0 $ ( 3 0 8 3 ? 4 8 0 8 3 ? 2 8 a 0 8 3 ? 2 8 a 0 8 3 ? 2 8 a # , + ? # # / 0 8 3 ? 4 2 ) ' ( 3 0 ! 0 8 3 ? 2 & ) . ( 3 0 ! 0 8 3 ? 2 8 a 0 8 3 ? 2 8 a 0 8 3 ? 2 8 a 0 8 3 ? 2 8 a 0 8 3 ? 2 8 a m s303 12v 1 6 3 3 6 $ $ pin description stm8tl5xxx 20/79 docid022344 rev 4 figure 5. stm8tl53f4p6 tssop20 20-pin package pinout 1. hs corresponds to 20 ma hi gh sink/source capability. 2. power supply pins must be correctly decoupled with capacitors near the pins. please refer to the power supply circuitry details in section 9.3.2: power supply on page 44 and the stm8tl5xxx reference manual (rm0312) section 6: power supply. figure 6. STM8TL52F4p6 tssop20 20-pin package pinout 1. hs corresponds to 20 ma hi gh sink/source capability. 2. power supply pins must be correctly decoupled with capacitors near the pins. please refer to the power supply circuitry details in section 9.3.2: power supply on page 44 and the stm8tl5xxx reference manual (rm0312) section 6: power supply. 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 12 11 9 10 pd6(hs)/pxs_tx6/tim3_ch1 pd5(hs)/pxs_tx5/tim2_ch2 pd4(hs)/pxs_tx4/tim2_ch1 pd1(hs)/pxs_tx1 pd0(hs)/pxs_tx0 pxs_rx7a pxs_rx6a pxs_rx2a pxs_rx1a pxs_rx0a tim3_trig/pxs_tx8/(hs)pb0 beep/swim/(hs)pa0 [tim3_ch1]/spi_nss/(hs)pa1 [tim3_ch2]/usart_ck/spi_sck/(hs)pa2 i2c_sda/usart_tx/spi_miso/(hs)pa3 i2c_scl/usart_rx/spi_mosi/(hs)pa4 vdd vss pxs_vreg nrst/(hs)pa5 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 12 11 9 10 pd6(hs)/tim3_ch1 pd5(hs)/tim2_ch2 pd4(hs)/tim2_ch1 pd1(hs)/pxs_tx1 pd0(hs)/pxs_tx0 pxs_rx7a pxs_rx6a pxs_rx2a pxs_rx1a pxs_rx0a tim3_trig/(hs)pb0 beep/swim/(hs)pa0 [tim3_ch1]/spi_nss/(hs)pa1 [tim3_ch2]/usart_ck/spi_sck/(hs)pa2 i2c_sda/usart_tx/spi_miso/(hs)pa3 i2c_scl/usart_rx/spi_mosi/(hs)pa4 vdd vss pxs_vreg nrst/(hs)pa5 docid022344 rev 4 21/79 stm8tl5xxx pin description 25 table 2. legends/abbreviations type i = input, o = output, s = power supply level input ft = 5 v tolerant, tc = 3 v capable output hs = high sink/source (20 ma) port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push-pull reset state bold x (pin state after reset release). unless otherwise specified, the pin stat e is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). table 3. stm8tl5xxx pin description pin no. pin name type input output main function (after reset) alternate function ufqfpn48 ufqfpn28 tssop20 level floating wpu ext. interrupt high sink/source od pp default remap 1 pb6/ pxs_tx14 i/o tc x xxhsxx port b6 proxsense transmit 14 2272 pa0 (1) /swim/ beep i/o tc x x xhsx x swim port a0 (1) swim input and output beep output 3283 pa1/spi_nss/ [tim3_ch1] i/o ft x xxhsxx port a1 spi master/ slave select timer 3 - channel 1 414 pa2/spi_sck/ usart_ck/ [tim3_ch2] (2) i/o ft x xxhsxx port a2 spi clock timer 3 - channel 2 usart synchronous clock 525 pa3/spi_miso/ usart_tx/ i2c_sda (2) i/o ft x xxhsxx port a3 spi master in/ slave out usart transmit i2c data pin description stm8tl5xxx 22/79 docid022344 rev 4 636 pa4/spi_mosi/ usart_rx/ i2c_scl i/o ft x xxhsxx port a4 spi master out/ slave in usart receive i2c clock 747vdd s digital power supply 858vss s digital ground 9 6 9 pxs_vreg s proxsense voltage regulator external decoupling capacitor 10 7 10 pa5/nrst (3) i/o tc hs x x reset port a5 (output only) 11 8 pa6/ pxs_trig/ clk_cco i/o ft x xxhsxx port a6 proxsense external trigger input clk clock output 12 9 pa7/pxs_rfin i/o tc x xxhsxx port a7 proxsense antenna input 13 10 11 pxs_rx0a pxs_rx0a proxsense receiver 0a 14 pxs_rx0b pxs_rx0b proxsense receiver 0b 15 11 12 pxs_rx1a pxs_rx1a proxsense receiver 1a 16 pxs_rx1b pxs_rx1b proxsense receiver 1b table 3. stm8tl5xxx pin description (continued) pin no. pin name type input output main function (after reset) alternate function ufqfpn48 ufqfpn28 tssop20 level floating wpu ext. interrupt high sink/source od pp default remap docid022344 rev 4 23/79 stm8tl5xxx pin description 25 17 12 13 pxs_rx2a pxs_rx2a proxsense receiver 2a 18 pxs_rx2b pxs_rx proxsense receiver 2b 19 13 pxs_rx3a pxs_rx3a proxsense receiver 3a 20 pxs_rx3b pxs_rx3b proxsense receiver 3b 21 14 pxs_rx4a pxs_rx4a proxsense receiver 4a 22 pxs_rx4b pxs_rx4b proxsense receiver 4b 23 15 pxs_rx5a pxs_rx5a proxsense receiver 5a 24 pxs_rx5b pxs_rx5b proxsense receiver 5b 25 16 14 pxs_rx6a pxs_rx6a proxsense receiver 6a 26 pxs_rx6b pxs_rx6b proxsense receiver 6b 27 17 15 pxs_rx7a pxs_rx7a proxsense receiver 7a 28 pxs_rx7b pxs_rx7b proxsense receiver 7b 29 pxs_rx8a pxs_rx8a proxsense receiver 8a 30 pxs_rx8b pxs_rx8b proxsense receiver 8b 31 pxs_rx9a pxs_rx9a proxsense receiver 9a 32 pxs_rx9b pxs_rx9b proxsense receiver 9b table 3. stm8tl5xxx pin description (continued) pin no. pin name type input output main function (after reset) alternate function ufqfpn48 ufqfpn28 tssop20 level floating wpu ext. interrupt high sink/source od pp default remap pin description stm8tl5xxx 24/79 docid022344 rev 4 33 18 16 pd0/pxs_tx0 i/o tc x xxhsxx port d0 proxsense transmitter 0 34 19 17 pd1/pxs_tx1 i/o tc x xxhsxx port d1 proxsense transmitter 1 35 20 pd2/pxs_tx2 (4) i/o tc x xxhsxx port d2 proxsense transmitter 2 (4) 36 21 pd3/pxs_tx3 (4) i/o tc x xxhsxx port d3 proxsense transmitter 3 (4) 37 vssio s ios ground 38 vddio s ios power supply 39 22 18 pd4/pxs_tx4 (4) / tim2_ch1 i/o tc x xxhsxx port d4 proxsense transmitter 4 (4) timer 2 - channel 1 40 23 19 pd5/pxs_tx5 (4) / tim2_ch2 i/o tc x xxhsxx port d5 proxsense transmitter 5 (4) timer 2 - channel 2 41 24 20 pd6/pxs_tx6 (4) / tim3_ch1 i/o tc x xxhsxx port d6 proxsense transmitter 6 (4) timer 3 - channel1 42 25 pd7/pxs_tx7 (4) / tim3_ch2 i/o tc x xxhsxx port d7 proxsense transmitter 7 (4) timer 3 - channel 2 43 26 1 pb0/pxs_tx8 (4) / tim3_etr i/o tc x xxhsxx port b0 proxsense transmitter 8 (4) timer 3 - external trigger table 3. stm8tl5xxx pin description (continued) pin no. pin name type input output main function (after reset) alternate function ufqfpn48 ufqfpn28 tssop20 level floating wpu ext. interrupt high sink/source od pp default remap docid022344 rev 4 25/79 stm8tl5xxx pin description 25 44 pb1 (2) /pxs_tx9 / tim2_etr i/o tc x xxhsxx port b1 proxsense transmitter 9 timer 2 - external trigger 45 pb2/pxs_tx10 i/o tc x xxhsxx port b2 proxsense transmitter 10 46 pb3/pxs_tx11 i/o tc x xxhsxx port b3 proxsense transmitter 11 47 pb4/pxs_tx12 i/o tc x xxhsxx port b4 proxsense transmitter 12 48 pb5/pxs_tx13 i/o tc x xxhsxx port b5 proxsense transmitter 13 1. the pa0/swim pin is in input pull-up du ring the reset phase and after reset release. 2. a pull-up is applied to pa2, pa3 and pb1 during the reset phas e. these three pins are input floating after reset release. 3. at power-up, the pa5/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa5), it can be configured only as output open-drain or pus h-pull, not as a general purpose input. refer to section configuring nrst/pa5 pin as general purpose output in the stm8tl5xxx reference manual (rm0312). 4. not available for stm8tl52xx. table 3. stm8tl5xxx pin description (continued) pin no. pin name type input output main function (after reset) alternate function ufqfpn48 ufqfpn28 tssop20 level floating wpu ext. interrupt high sink/source od pp default remap memory and register map stm8tl5xxx 26/79 docid022344 rev 4 5 memory and register map figure 7. memory map 1. refer to table 5 for an overview of hardware register mapping, to table 4 for details on i/o port hardware registers, and to table 6 for information on cpu/swim/ debug module controller registers. ms19123v1 ram (4 kbytes) (1) including stack reserved option bytes reserved unique id reserved gpio and peripheral registers (1) reserved cpu/swim/debug/itc registers interrupt vectors low-density flash program memory (up to 16 kbytes) (1) including data eeprom (up to 2 kbytes) 0x00 0000 0x00 0fff 0x00 1000 0x00 47ff 0x00 4800 0x00 48ff 0x00 4900 0x00 4924 0x00 4925 0x00 4930 0x00 4931 0x00 49ff 0x00 5000 0x00 57ff 0x00 5800 0x00 7eff 0x00 7f00 0x00 7fff 0x00 8000 0x00 807f 0x00 8080 0x00 bfff docid022344 rev 4 27/79 stm8tl5xxx memory and register map 37 figure 8. flash and ram boundary addresses memory area size start address end address ram 4 kbytes 0x00 0000 0x00 0fff flash program memory 16 kbytes 0x00 8000 0x00 bfff table 4. i/o port ha rdware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data outp ut latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a to 0x00 500e reserved area (5 bytes) 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 memory and register map stm8tl5xxx 28/79 docid022344 rev 4 table 5. general hardware register map address block register label register name reset status 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection register 0x00 0x00 5053 flash _dukr data eeprom unprotection register 0x00 0x00 5054 flash _iapsr flash in-applicat ion programming status register 0xx0 0x00 5055 to 0x00 509d reserved area (73 bytes) 0x00 509e syscfg syscfg_rmpcr1 remappi ng control register 1 0x00 0x00 509f reserved area (1 byte) 0x00 50a0 itc-exti exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf external interrupt port select register 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 to 0x00 50af reserved area (8 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 (1) 0x00 50b2 to 0x00 50bf reserved area (14 bytes) 0x00 50c0 clk clk_ckdivr clock divider register 0x00 0x00 50c1 to 0x00 50c2 reserved area (2 bytes) 0x00 50c3 clk_pckenr1 peripheral clock gating register 1 0x00 0x00 50c4 clk_pckenr2 peripheral clock gating register 2 0x01 0x00 50c5 clk_ccor configurable clock control register 0x10 0x00 50c6 to 0x00 50d2 reserved area (12 bytes) 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdg window register 0x00 50d5 to 0x00 50d7 reserved area (11 bytes) docid022344 rev 4 29/79 stm8tl5xxx memory and register map 37 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr awu control/status register 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep cont rol/status register 0x1f 0x00 50f4 to 0x00 51ff reserved area (268 bytes) 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interr upt control register 0x00 0x00 5203 spi_sr spi status register 0x00 0x00 5204 spi_dr spi data register 0x00 0x00 5205 to 0x00 520f reserved area (11 bytes) 0x00 5210 i2c i2c_cr1 i2c control register 1 0x00 0x00 5211 i2c_cr2 i2c control register 2 0x00 0x00 5212 i2c_freqr i2c frequency register 0x00 0x00 5213 i2c_oar1l i2c own address register 1 low 0x00 0x00 5214 i2c_oar1h i2c own address register 1 high 0x00 0x00 5215 i2c_oar2 i2c own address register 2 0x00 0x00 5216 i2c_dr i2c data register 0x00 0x00 5217 i2c_sr1 i2c status register 1 0x00 0x00 5218 i2c_sr2 i2c status register 2 0x00 0x00 5219 i2c_sr3 i2c status register 3 0x00 0x00 521a i2c_itr i2c interrupt control register 0x00 0x00 521b i2c_ccrl i2c clock control register low 0x00 0x00 521c i2c_ccrh i2c clock control register high 0x00 0x00 521d i2c_triser i2c trise register 0x00 0x00 521e to 0x00 522f reserved area (18 bytes) table 5. general hardware register map (continued) address block register label register name reset status memory and register map stm8tl5xxx 30/79 docid022344 rev 4 0x00 5230 usart usart_sr usart status register 0xc0 0x00 5231 usart_dr usart data register 0xxx 0x00 5232 usart_brr1 usart baud rate register 1 0x00 0x00 5233 usart_brr2 usart baud rate register 2 0x00 0x00 5234 usart_cr1 usart control register 1 0x00 0x00 5235 usart_cr2 usart control register 2 0x00 0x00 5236 usart_cr3 usart control register 3 0x00 0x00 5237 usart_cr4 usart control register 4 0x00 0x00 5238 to 0x00 524f reserved area (18 bytes) 0x00 5250 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_ier tim2 interrupt enable register 0x00 0x00 5255 tim2_sr1 tim2 status register 1 0x00 0x00 5256 tim2_sr2 tim2 status register 2 0x00 0x00 5257 tim2_egr tim2 event generation register 0x00 0x00 5258 tim2_ccmr1 tim2 captur e/compare mode register 1 0x00 0x00 5259 tim2_ccmr2 tim2 captur e/compare mode register 2 0x00 0x00 525a tim2_ccer1 tim2 capture/ compare enable register 1 0x00 0x00 525b tim2_cntrh tim2 co unter register high 0x00 0x00 525c tim2_cntrl tim2 counter register low 0x00 0x00 525d tim2_pscr tim2 prescaler register 0x00 0x00 525e tim2_arrh tim2 auto-reload register high 0xff 0x00 525f tim2_arrl tim2 auto-reload register low 0xff 0x00 5260 tim2_ccr1h tim2 captur e/compare register 1 high 0x00 0x00 5261 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5262 tim2_ccr2h tim2 captur e/compare register 2 high 0x00 0x00 5263 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5264 tim2_bkr tim2 break register 0x00 0x00 5265 tim2_oisr tim2 outpu t idle state register 0x00 0x00 5266 to 0x00 527f reserved area (26 bytes) table 5. general hardware register map (continued) address block register label register name reset status docid022344 rev 4 31/79 stm8tl5xxx memory and register map 37 0x00 5280 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_ier tim3 interrupt enable register 0x00 0x00 5285 tim3_sr1 tim3 status register 1 0x00 0x00 5286 tim3_sr2 tim3 status register 2 0x00 0x00 5287 tim3_egr tim3 event generation register 0x00 0x00 5288 tim3_ccmr1 tim3 captur e/compare mode register 1 0x00 0x00 5289 tim3_ccmr2 tim3 captur e/compare mode register 2 0x00 0x00 528a tim3_ccer1 tim3 capture/ compare enable register 1 0x00 0x00 528b tim3_cntrh tim3 co unter register high 0x00 0x00 528c tim3_cntrl tim3 counter register low 0x00 0x00 528d tim3_pscr tim3 prescaler register 0x00 0x00 528e tim3_arrh tim3 auto-reload register high 0xff 0x00 528f tim3_arrl tim3 auto-reload register low 0xff 0x00 5290 tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 5291 tim3_ccr1l tim3 capture/compare register 1 low 0x00 0x00 5292 tim3_ccr2h tim3 captur e/compare register 2 high 0x00 0x00 5293 tim3_ccr2l tim3 capture/compare register 2 low 0x00 0x00 5294 tim3_bkr tim3 break register 0x00 0x00 5295 tim3_oisr tim3 outpu t idle state register 0x00 0x00 5296 to 0x00 52df reserved area (74 bytes) 0x00 52e0 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_ier tim4 interrupt enable register 0x00 0x00 52e4 tim4_sr1 tim4 status register 1 0x00 0x00 52e5 tim4_egr tim4 event generation register 0x00 0x00 52e6 tim4_cntr tim4 counter register 0x00 0x00 52e7 tim4_pscr tim4 prescaler register 0x00 0x00 52e8 tim4_arr tim4 auto -reload register low 0xff 0x00 52e9 to 0x00 52ff reserved area (23 bytes) table 5. general hardware register map (continued) address block register label register name reset status memory and register map stm8tl5xxx 32/79 docid022344 rev 4 0x00 5300 pxs pxs_cr1 proxsense control register 1 0x00 0x00 5301 pxs_cr2 proxsense control register 2 0x00 0x00 5302 pxs_cr3 proxsense control register 3 0x04 0x00 5303 reserved area (1 byte) 0x00 5304 pxs_isr proxsense interr upt and status register 0x00 0x00 5305 reserved area (1 byte) 0x00 5306 pxs_ckcr1 proxsense cl ock control register 1 0x30 0x00 5307 pxs_ckcr2 proxsense cl ock control register 2 0x11 0x00 5308 pxs_rxenrh proxsense receiver enable register high 0x00 0x00 5309 pxs_rxenrl proxsense rece iver enable register low 0x00 0x00 5310 to 0x00 5311 reserved area (2 bytes) 0x00 530a pxs pxs_rxcr1h proxsense receiver control register 1 high 0x00 0x00 530b pxs_rxcr1l proxsense receiv er control regi ster 1 low 0x00 0x00 530c pxs_rxcr2h proxsense receiv er control register 2 high 0x00 0x00 530d pxs_rxcr2l proxsense receiv er control regi ster 2 low 0x00 0x00 530e pxs_rxcr3h proxsense receiv er control register 3 high 0x00 0x00 530f pxs_rxcr3l prox sense receiver contro l register 3 low 0x00 0x00 5312 pxs_rxinsrh proxsense receiv er inactive state register high 0x00 0x00 5313 pxs_rxinsrl proxsense receiver inactive state register low 0x00 0x00 5314 to 0x00 5315 reserved area (2 bytes) 0x00 5316 pxs pxs_txenrh proxsense transmit enable register high 0x00 0x00 5317 pxs_txenrl proxsense trans mit enable register low 0x00 0x00 5318 to 0x00 5319 reserved area (2 bytes) 0x00 531a pxs pxs_maxrh proxsense maximum count er value register high 0xff 0x00 531b pxs_maxrl proxsense maximum counter value register low 0xff 0x00 531c pxs_maxenrh proxsense maximum counter enable re gister high 0x00 0x00 531d pxs_maxenrl proxsense maximu m counter enable register low 0x00 0x00 531e pxs_rxsrh proxsense receiver status register high 0x00 0x00 531f pxs_rxsrl proxsense receiv er status register low 0x00 0x00 5320 pxs_rx0cntrh proxsense counter register receiver channel high 0x00 0x00 5321 pxs_rx0cntrl proxsense counter register receiver channel low 0x00 0x00 5322 pxs_rx1cntrh proxsense counter register receiver channel high 0x00 0x00 5323 pxs_rx1cntrl proxsense counter register receiver channel low 0x00 0x00 5324 pxs_rx2cntrh proxsense counter register receiver channel high 0x00 table 5. general hardware register map (continued) address block register label register name reset status docid022344 rev 4 33/79 stm8tl5xxx memory and register map 37 0x00 5325 pxs pxs_rx2cntrl proxsense counter register receiver channel low 0x00 0x00 5326 pxs_rx3cntrh proxsense counter register receiver channel high 0x00 0x00 5327 pxs_rx3cntrl proxsense counter register receiver channel low 0x00 0x00 5328 pxs_rx4cntrh proxsense counter register receiver channel high 0x00 0x00 5329 pxs_rx4cntrl proxsense counter register receiver channel low 0x00 0x00 532a pxs_rx5cntrh proxsense counter register receiver channel high 0x00 0x00 532b pxs_rx5cntrl proxsense counter register receiver channel low 0x00 0x00 532c pxs_rx6cntrh proxsense counter register receiver channel high 0x00 0x00 532d pxs_rx6cntrl proxsense counter register receiver channel low 0x00 0x00 532e pxs_rx7cntrh proxsense counter register receiver channel high 0x00 0x00 532f pxs_rx7cntrl proxsense counter register receiver channel low 0x00 0x00 5330 pxs_rx8cntrh proxsense counter register receiver channel high 0x00 0x00 5331 pxs_rx8cntrl proxsense counter register receiver channel low 0x00 0x00 5332 pxs_rx9cntrh proxsense counter register receiver channel high 0x00 0x00 5333 pxs_rx9cntrl proxsense counter register receiver channel low 0x00 0x00 5334 to 0x00 533f reserved area (12 bytes) 0x00 5340 pxs pxs_rx0csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5341 pxs_rx1csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5342 pxs_rx2csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5343 pxs_rx3csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5344 pxs_rx4csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5345 pxs_rx5csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5346 pxs_rx6csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5347 pxs_rx7csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5348 pxs_rx8csselr proxsense receiver sampling capacitor selection register 0x00 0x00 5349 pxs_rx9csselr proxsense receiver sampling capacitor selection register 0x00 0x00 534a to 0x00 534f reserved area (6 bytes) table 5. general hardware register map (continued) address block register label register name reset status memory and register map stm8tl5xxx 34/79 docid022344 rev 4 0x00 5350 pxs pxs_rx0epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5351 pxs_rx1epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5352 pxs_rx2epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5353 pxs_rx3epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5354 pxs_rx4epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5355 pxs_rx5epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5356 pxs_rx6epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5357 pxs_rx7epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5358 pxs_rx8epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 5359 pxs_rx9epccselr proxsense receiver electrode parasitic compensation capacitor selection register 0x00 0x00 535a to 0x00 7eff reserved area (11174 bytes) 1. after power-on reset. table 5. general hardware register map (continued) address block register label register name reset status table 6. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x80 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x05 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a cc condition code register 0x28 docid022344 rev 4 35/79 stm8tl5xxx memory and register map 37 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cfg cfg_gcr global configuration register 0x00 0x00 7f61 0x00 7f6f reserved area (15 bytes) 0x00 7f70 itc-spr (1) itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 debug module control register 1 0x00 0x00 7f97 dm_cr2 debug module control register 2 0x00 0x00 7f98 dm_csr1 debug module control/status register 1 0x10 0x00 7f99 dm_csr2 debug module control/status register 2 0x00 0x00 7f9a dm_enfctr enable function register 0xff 1. refer to table 5: general hardware register map on page 28 (addresses 0x00 50a0 to 0x00 50a5) for a list of external interrupt registers. table 6. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status interrupt vector mapping stm8tl5xxx 36/79 docid022344 rev 4 6 interrupt vector mapping table 7. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt - - - - 0x00 8004 0 reserved 0x00 8008 1flash flash end of programing/ write attempted to protected page interrupt - - yes yes 0x00 800c 2 pxs end of conversion/first conversion completed -yes (2) yes yes 0x00 8010 3 reserved 0x00 8011 -0x00 8017 4 awu auto wakeup from halt - yes yes yes 0x00 8018 5 reserved 0x00 801c 6 extib external interrupt port b yes yes yes yes 0x00 8020 7 extid external interrupt port d yes yes yes yes 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes 0x00 8044 16 reserved 0x00 8048 17 reserved 0x00 804c -0x00 804f 18 reserved 0x00 8050 19 tim2 tim2 update/overflow/ trigger/break interrupt - - yes yes 0x00 8054 20 tim2 tim2 capture/compare interrupt - - yes yes 0x00 8058 21 tim3 tim3 update/overflow/ trigger/break interrupt - - yes yes 0x00 805c docid022344 rev 4 37/79 stm8tl5xxx interrupt vector mapping 37 22 tim3 tim3 capture/compare interrupt - - yes yes 0x00 8060 23- 24 reserved 0x00 8064- 0x00 806b 25 tim4 tim4 update/overflow/ trigger interrupt - - yes yes 0x00 806c 26 spi spi tx buffer empty/ rx buffer not empty/ error/wakeup interrupt yes yes yes yes 0x00 8070 27 usart usart transmit data register empty/ transmission complete interrupt - - yes yes 0x00 8074 28 usart usart received data ready/overrun error/ idle line detected/parity error/global error interrupt - - yes yes 0x00 8078 29 i2c i2c interrupt (3) yes yes yes yes 0x00 807c 1. the low power wait mode is entered when executing a wfe instruction in low power run mode. in wfe mode, the interrupt is served if it has been previously enabled. after processing the interrupt, the pr ocessor goes back to wfe mode. when the interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. 2. proxsense activated before executing halt instruction. 3. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 7. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address option bytes stm8tl5xxx 38/79 docid022344 rev 4 7 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated row of the memory. all option bytes can be modified only in icp mode (with swim) by accessing the eeprom address. see table 8 for details on option byte addresses. refer to the stm8tl5xxx flash programming manual (pm0212) and stm8 swim and debug manual (um0470) for information on swim programming procedures. table 8. option bytes addr. option name option byte no. option bits factory default setting 7654 3 2 1 0 0x4800 read-out protection (rop) opt0 rop[7:0] 0xaa 0x4801 - - must be programmed to 0x00 0x00 0x4802 user boot code size (ubc) opt1 ubc[7:0] 0x00 0x4803 datasize opt2 datasize[7:0] 0x00 0x4807 pcodesize opt3 pcodesize[7:0] 0x00 0x4808 window watchdog and independent window watchdog opt4 [3:0] reserved wwdg _halt wwdg _hw iwdg _halt iwdg _hw 0x00 table 9. option byte description option byte number description opt0 rop[7:0] memory readout protection (rop) 0xaa: readout protection disabled (write access via swim protocol) refer to read-out protection section in the stm8tl5xxx reference manual (rm0312) for details. opt1 ubc[7:0] size of the user boot code area 0x00: no ubc 0x01-0x02: ubc contains only the interrupt vectors. 0x03: page 0 and 1 reserved for the interrupt vectors. page 2 is available to store user boot co de. memory is write protected ... 0xff: page 0 to 254 reserved for ubc, memory is write protected refer to user boot area (ubc) section in the stm8tl5xxx reference manual (rm0312) for more details. docid022344 rev 4 39/79 stm8tl5xxx option bytes 39 caution: after a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. opt2 datasize[7:0] size of the data eeprom area 0x00: no data eeprom area 0x01: 1 page reserved for data storage from 0xbfc0 to 0xbfff 0x02: 2 pages reserved for data storage from 0xbf80 to 0xbfff ... 0x20: 32 pages reserved for data storage from 0xb800 to 0xbfff refer to data eeprom (data) section in the st m8tl5xxx reference manual (rm0312) for more details. opt3 pcodesize[7:0] size of the proprietary code area 0x00: no proprietary code area 0x03: trap vector and page 2 (0x8080 to 0x80bf) reserved for the proprietary code and read/write protected ... 0xff: trap vector and page 2 to 254 (0x8080 to 0xbfbf) reserved for the proprietary code an d read/write protected refer to proprietary code area (pcode) section in the stm8tlxxxx programming manual(pm0212) for more details. opt4 iwdg_hw: independent watchdog 0: independent watchdog activated by software 1: independent watchdog activated by hardware iwdg_halt: independent window watchdog reset on halt/active-halt 0: independent watchdog continues r unning in halt/active-halt mode 1: independent watchdog stopped in halt/active-halt mode wwdg_hw: window watchdog 0: window watchdog activated by software 1: window watchdog activated by hardware wwdg_halt: window watchdog reset on halt/active-halt 0: window watchdog stopped in halt/active-halt mode 1: window watchdog continues running in halt/active-halt mode table 9. option byte description (continued) option byte number description unique id stm8tl5xxx 40/79 docid022344 rev 4 8 unique id stm8tl5xxx devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: ? for use as serial numbers ? for use as security keys to increase the code security in the program memory while using and combining this unique id with software cryptograp hic primitives and protocols before programming the internal memory ? to activate secure boot processes table 10. unique id registers (96 bits) address content description unique id bits 7654 3 2 1 0 0x4925 x coordinate on the wafer u_id[7:0] 0x4926 u_id[15:8] 0x4927 y coordinate on the wafer u_id[23:16] 0x4928 u_id[31:24] 0x4929 wafer number u_id[39:32] 0x492a lot number u_id[47:40] 0x492b u_id[55:48] 0x492c u_id[63:56] 0x492d u_id[71:64] 0x492e u_id[79:72] 0x492f u_id[87:80] 0x4930 u_id[95:88] docid022344 rev 4 41/79 stm8tl5xxx electrical parameters 68 9 electrical parameters 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature of t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 9.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3 v. they are given only as design guidelines and are not tested. 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . figure 9. pin loading conditions 50 pf stm8tl5xxx pin electrical parameters stm8tl5xxx 42/79 docid022344 rev 4 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 10. pin input voltage 9.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. ex posure to maximum rating conditions for extended periods may affect device reliability. v in stm8tl5xxx pin table 11. voltage characteristics symbol ratings min max unit v dd - v ss external supply voltage (including v dd and v ddio ) (1) 1. all power (v dd , v ddio ) and ground (v ss , v ssio ) pins must always be connected to the external power supply. ? 0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 12. for maximum allowed injected current values. receiver channel pins (pxs_rx0a...rx9b) v ss ? 0.3 pxs_v reg ( 1.45) input voltage on pb0...7 and pd0...7 (3) 3. current injection on these pins is not allowed. pins used as general purpose i/o v ss ? 0.3 4.0 pins used as transmitter channel pins (pxs_tx0..pxs_tx15) v ss ? 0.3 pxs_v reg ( 1.45) input voltage on any pa pins v ss ? 0.3 4.0 v esd electrostatic discharge voltage see absolute maximum ratings (e lectrical sensitivity) on page 67 docid022344 rev 4 43/79 stm8tl5xxx electrical parameters 68 9.3 operating conditions subject to general operating conditions for v dd and t a . 9.3.1 general operating conditions table 12. current characteristics symbol ratings max. unit i vdd total current into v dd power line (source) 80 ma i vss total current out of v ss ground line (sink) 80 i io output current sunk by any other i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (1) 1. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in docid022344 rev 4 45/79 stm8tl5xxx electrical parameters 68 9.3.4 proxsense regulator voltage 9.3.5 supply current characteristics total current consumption the mcu is placed under the following conditions: ? all i/o pins in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept if explicitly mentioned subject to general operating conditions for v dd and t a . table 16. proxsense voltage regulator characteristics symbol parameter conditions min. typ. max. unit c reg (1) 1. the capacitor must be routed as close as pxs_vreg as possible ( 1cm) voltage regulator decoupling capacitance (2) 2. equivalent serial resistor 1 ? -0.5110f v reg regulated voltage during acquisition - - 1.45 - v table 17. total current consumption in run mode (1) 1. based on characterization results, unless otherwise specified. symbol parameter conditions (2) 2. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc oscillator, f cpu =f master. typ. max. (3) 3. maximum values are given for t a = ? 40 to 85 c. unit i dd (run) supply current in run mode code executed from ram f master = 2 mhz 0.4 0.6 ma f master = 4 mhz 0.55 0.7 f master = 8 mhz 0.9 1.2 f master = 16 mhz 1.6 2.1 (4) 4. tested in production. code executed from flash f master = 2 mhz 0.56 0.7 f master = 4 mhz 0.88 1.8 f master = 8 mhz 1.5 2.5 f master = 16 mhz 2.8 3.5 electrical parameters stm8tl5xxx 46/79 docid022344 rev 4 figure 12. i dd(run) vs. v dd , f cpu = 16 mhz 1. typical current consumption meas ured with code executed from flash. table 18. total current consumption in wait mode (1) 1. based on characterization results, unless otherwise specified. symbol parameter conditions typ. max. (2) 2. maximum values are given for t a = ? 40 to 85 c. unit i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, hsi internal rc osc f master = 2 mhz 260 400 a f master = 4 mhz 300 450 f master = 8 mhz 380 600 f master = 16 mhz 500 800 6 $ $ 6 ) $ $ 2 u n ( 3 ) - ( z m ! 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 1.5 2 2.5 3 3.5 4 25c 90c -40c . 4 7 docid022344 rev 4 47/79 stm8tl5xxx electrical parameters 68 figure 13. i dd(wait) vs. v dd. f cpu = 16 mhz 1. typical current consumption meas ured with code executed from ram. 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2. 5 33.54 dd (v) 25 c 90 c -40 c i (w a it) h s i 16 mhz (ma) m s 19199v1 v dd electrical parameters stm8tl5xxx 48/79 docid022344 rev 4 figure 14. typ. i dd(halt) vs. v dd. f cpu = 2 mhz and 16 mhz 1. typical current consumption meas ured with code executed from flash. table 19. total current consumption in halt mode and active-halt mode v dd = 1.65 v to 3.6 v (1) (2) 1. t a = ? 40 to 85 c, no floating i/o, unless otherwise specified. 2. data based on characterization, not tested in production. symbol parameter condi tions typ. max. unit i dd(ah) supply current in active-halt mode lsi rc osc. (at 38 khz) t a = ? 40 c to 25 c 1 2 a t a = 85 c 1.4 3.2 a i dd(wuprox) supply current during wakeup time from active halt mode (using hsi) f cpu = 16 mhz 2 - ma t wu(ah) (3) 3. measured from interrupt event to interrupt vector fetch. to get t wu for another cpu frequency use t wu (freq) = t wu (16 mhz) + 1.5 (t freq -t 16 mhz ). the first word of interrupt routine is fetched 5 cpu cycles after t wu . wakeup time from active- halt mode to run mode f cpu = 16 mhz 4 6.5 s i dd(halt) supply current in halt mode t a = ? 40 c to 25 c 0.4 1.2 (4) 4. tested in production. a t a = 85 c 1 2.5 (4) a i dd(wufh) supply current during wakeup time from halt mode f cpu = 16 mhz 2 - ma t wu(halt) wakeup time from halt mode to run mode f cpu = 16 mhz 4 6.5 s 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 0.0009 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v dd (v) 25 c 90 c - 40 c ) ( a l t m ( z m ! - 3 6 $ $ docid022344 rev 4 49/79 stm8tl5xxx electrical parameters 68 current consumption of on-chip peripherals measurement made for f master = from 2 mhz to 16 mhz current consumption with proxsense peripherals measurement made for f master = 16 mhz, f proxsense = 16 mhz, all other peripherals off and under the following conditions: pxs_rx i csselr (sampling capacitor) = 0x10 pxs_rx i epccselr ( electrode parasitic capacitance compensation) = 0x80 capacitance between tx and rx of 10nf table 20. peripheral current consumption symbol parameter typ. v dd = 3.0 v unit i dd(tim2) tim2 supply current (1) 1. data based on a differential i dd measurement between all peripherals off and a timer counter running at 16 mhz. the cpu is in wait mode in both cases. no ic/oc programmed, no i/o pin toggling. not tested in production. 9 a/mhz i dd(tim3) tim3 supply current (1) 9 i dd(tim4) tim4 timer supply current (1) 4 i dd(usart) usartsupply current (2) 2. data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. the cpu is in wait mode in both cases. no i/o pin toggling. not tested in production. 7 i dd(spi) spi supply current (2) 4 i dd(i2c) i2c supply current (2) 4 table 21. proxsense peripheral current consumption (1) 1. data based on characterization, not tested in production symbol proxsense transmitter tx proxsense receiver rx typical unit i dd(pxs) 110.6 ma 141.1 1102.3 electrical parameters stm8tl5xxx 50/79 docid022344 rev 4 9.3.6 clock and ti ming characteristics internal clock source the parameters given in table 22 are derived from tests performed under ambient temperature and v dd supply voltage. they are subject to general operating conditions for v dd and t a . high speed internal rc oscillator figure 15. typical hsi frequency vs. v dd table 22. hsi oscillator characteristics (1) 1. v dd = 3v, t a = ? 40 to 125 c, unless otherwise specified. symbol parameter conditions min. typ. max. unit f hsi frequency v dd = 3.0 v - 16 - mhz acc hsi accuracy of hsi oscillator (factory calibrated) v dd = 3.0 v, t a = 25 c ? 1- 1 % 1.65 v vdd 3.6 v, t a = -40 to 85c ? 3- 3 % i dd(hsi) hsi oscillator power consumption - 70 100 a $ $ ) 4 * g s f r v f o d z < . ) [ > - 3 6 6 ; 6 = 15 15.2 15.4 15.6 15.8 16 16.2 16.4 16.6 16.8 17 1.522.533.54 25c 90c -40c docid022344 rev 4 51/79 stm8tl5xxx electrical parameters 68 figure 16. typical hsi accuracy vs. temperature, vdd = 3 v high speed proxsense rc oscillator low speed internal rc oscillator (lsi) table 23. hsi_pxs oscillator characteristics (1) 1. v dd = 3v, t a = ? 40 to 85 c, unless otherwise specified. symbol parameter conditions min. typ. max. unit f hsi_pxs frequency v dd = 3.0 v - 16 mhz table 24. lsi oscillator characteristics (1) 1. v dd = 1.65 v to 3.6 v, t a = ? 40 to 85c unless otherwise specified. symbol parameter conditions min. typ. max. unit f lsi frequency 26 38 56 khz f drift(lsi) lsi oscillator frequency drift (2) 2. for each individual part, this value is the frequency drift from the initial measured frequency . 0 c t a 85c ? 12 - 11 % ai17021 -5.0% -4.5% -4.0% -3.5% -3.0% -2.5% -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 temperature (c) rc accuracy 3v min 3v typical 3v max electrical parameters stm8tl5xxx 52/79 docid022344 rev 4 figure 17. typical lsi frequency vs. v dd 9.3.7 memory characteristics t a = ? 40 to 85c unless otherwise specified. ram characteristics flash memory characteristics $ $ - 4 * g s f r v f o d z < . ) [ > - 3 6 6 ; 6 = 26 28 30 32 34 36 38 1.5 2 2.5 3 3.5 4 25c 90c -40c table 25. ram and hardware registers symbol parameter conditions min. typ. max. unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by characterization, not tested in production. halt mode (or reset) 1.4 - - v table 26. flash program memory symbol parameter conditions min. typ. max. (1) unit v dd operating voltage (all modes, read/write/erase) f master = 16 mhz 1.65 - 3.6 v t prog programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) -6-ms programming time for 1 to 64 bytes (block) write cycles (on erased byte) -3-ms i prog programming/ erasing consumption t a = +25 c, v dd = 3.0 v - 0.7 - ma t a = +25 c, v dd = 1.8 v - - 1. data based on characterization re sults, not tested in production. docid022344 rev 4 53/79 stm8tl5xxx electrical parameters 68 table 27. program memory endurance & retention parameter conditions min. typ. max. unit endurance t a = ?40 to 85c 10 (1) 1. data based on characterization results, not tested in production. - - kcycles data retention 10 kcycles at t a = 85c 30 (1) - - years table 28. data memory endurance & retention parameter conditions min. typ. max. unit endurance t a = ? 40 to 85c 300 (1)(2) 1. data based on characterization results, not tested in production. 2. data based on characterization perform ed on the whole data memory (2 kbytes). - - kcycles data retention 300 kcycles at t a = 85c 30 (1) --years electrical parameters stm8tl5xxx 54/79 docid022344 rev 4 9.3.8 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. figure 18. typical pul l-up resistance r pu vs. v dd with v in =v ss table 29. i/o static characteristics (1) symbol parameter conditions min. typ. max. unit v il input low level voltage (2) standard i/os v ss ? 0.3 - 0.3 x v dd v v ih input high level voltage (2) standard i/os 0.70 x v dd -v dd +0.3 v hys schmitt trigger voltage hysteresis (3) standard i/os - 200 - mv i lkg input leakage current (4) v ss v in v dd --50 na v ss v in v reg rx,tx i/os --50 r pu weak pull-up equivalent resistor (5) v in = v ss 30 45 60 k c io (6) i/o pin capacitance - 5 - pf 1. v dd = 3.0 v, t a = ? 40 to 85 c unless otherwise specified. 2. data based on characterization re sults, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the maximum value may be exceeded if negative current is injected on adjacent pins. 5. r pu pull-up equivalent resistor based on a resistive transistor (corresponding i pu current characteristics. 6. data guaranteed by design, not tested in production. 25 30 35 40 45 50 1.5 2 2.5 3 3.5 4 6 ; 6 = 25c 90c -40c $ $ - 3 6 1 v m m 6 q s f t j t u b o d f < l0 > docid022344 rev 4 55/79 stm8tl5xxx electrical parameters 68 figure 19. typical v il and v ih vs v dd 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 1.5 2 2.5 3 3.5 4 25c 90c -40c $ $ - 3 6 6 ; 6 = 7 * - 7 * ) ; 7 = b o e electrical parameters stm8tl5xxx 56/79 docid022344 rev 4 output driving current subject to general operating conditions for v dd and t a unless otherwise specified. figure 20. typ. v ol at v dd = 1.8 v (standard ports) table 30. output driving current (high sink ports) i/o type symbol parameter conditions min. max. unit standard v ol (1) output low level voltage for an i/o pin i io = +2 ma, v dd = 1.8 v -0.45 v i io = +2 ma, v dd = 3.0 v -0.45 i io = +10 ma, v dd = 3.0 v -0.7 v oh (2) output high level voltage for an i/o pin i io = ? 1 ma, v dd = 1.8 v v dd -0.45 - i io = ? 1 ma, v dd = 3.0 v v dd -0.45 - i io = ? 10 ma, v dd = 3.0 v v dd -0.7 - proxsense i/o v oh output high level voltage for pxs_tx proxsense i/o i pxs_tx = 0.2 ma v reg - v oh output high level voltage for pxs_rx proxsense i/o i pxs_rx = 0.1 ma v reg - 1. the i io current sunk must always respect the absolute maximum rating and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating and the sum of i io (i/o ports and control pins) must not exceed i vdd . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 123456789 25c 90c -40c / , 7 ; 7 = - 3 6 ) ; m ! = 0 - docid022344 rev 4 57/79 stm8tl5xxx electrical parameters 68 figure 21. typ. v ol at v dd = 3.0 v (standard ports) figure 22. typ. v dd - v oh at v dd = 1.8 v(standard ports) / , 7 ; 7 = - 3 6 ) ; m ! = 0 - 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 2 4 6 8 10 12 14 16 18 20 25c 90c -40c / ( - 3 6 ) ; m ! = 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 012345678 25c 90c -40c 7 % % 7 0 ) ; 7 = electrical parameters stm8tl5xxx 58/79 docid022344 rev 4 figure 23. typ. v dd - v oh at v dd = 3.0 v (standard ports) figure 24. typ. v dd - v oh at v dd = 1.8 v (proxsense_tx ports) / ( - 3 6 ) ; m ! = 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 024681012141618 25c 90c -40c 7 % % 7 0 ) ; 7 = - 3 6 1 1.1 1.2 1.3 1.4 1.5 1.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 25c 90c -40c 7 0 ) ; 7 = * 0 ) ; n " = docid022344 rev 4 59/79 stm8tl5xxx electrical parameters 68 figure 25. typ. v dd - v oh at v dd = 1.8v (proxsense rx ports) / ( 7 ; 7 = - 3 6 ) ; m ! = 0 ) 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 25c 90c -40c electrical parameters stm8tl5xxx 60/79 docid022344 rev 4 nrst pin the nrst pin input driver is cmos. a permanent pull-up is present which is the same as r pu (see table 29 on page 54 ). subject to general operating conditions for v dd and t a unless otherwise specified. the reset network shown in figure 27 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in table 31 . otherwise the reset is not taken into account internally. figure 26. typical nrst pull-up resistance r pu vs. v dd table 31. nrst pin characteristics symbol parameter conditions min. typ. (1) 1. data based on characterization results, not tested in production. max. unit v il(nrst) nrst input low level voltage (1) v ss -0.8 v v ih(nrst) nrst input high level voltage (1) 1.4 - v dd v ol(nrst) nrst output low level voltage i ol = 2 ma - - v dd - 0.8 r pu(nrst) nrst pull-up equivalent resistor (2) 2. the r pu pull-up equivalent resistor is based on a resistive transistor. 30 45 60 k v f(nrst) nrst input filtered pulse (3) 3. data guaranteed by design, not tested in production. --50 ns t op(nrst) nrst output pulse width 20 - - v nf(nrst) nrst input not filtered pulse (3) 300 - - $ $ - 3 6 6 ; 6 = 25 30 35 40 45 50 1.5 2 2.5 3 3.5 4 25c 90c -40c 1 v m m 6 q s f t j t u b o d f < l0 > docid022344 rev 4 61/79 stm8tl5xxx electrical parameters 68 figure 27. recommended nrst pin configuration the reset network shown in figure 27 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in table 31 . otherwise the reset is not taken into account internally. for power consumption sensitive applications, t he capacity of the external reset capacitor can be reduced to limit the charge/discharge curr ent. if the nrst signal is used to reset the external circuitry, the user must pay attenti on to the charge/discharge time of the external capacitor to meet the reset timing conditi ons of the external devices. the minimum recommended capacity is 10 nf. 0.1 f external reset circuit stm8tl5xxx filter r pu v dd internal reset rstin electrical parameters stm8tl5xxx 62/79 docid022344 rev 4 9.3.9 communication interfaces serial peripheral interface (spi) the parameters given in table 32 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions summarized in section 9.3.1 on page 43 , unless otherwise specified. refe r to i/o port characteristics for more details on the input/output alternate function characterist ics (nss, sck, mosi, miso). table 32. spi characteristics symbol parameter conditions (1) min. max. unit f sck 1/t c(sck) spi clock frequency master mode 0 8 mhz slave mode 0 8 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 30 ns t su(nss) (2) nss setup time slave mode 4 x t master - t h(nss) (2) nss hold time slave mode 80 - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f master = 8 mhz, f sck = 4 mhz 105 145 t su(mi) (2) t su(si) (2) data input setup time master mode 30 - slave mode 3 - t h(mi) (2) t h(si) (2) data input hold time master mode 15 - slave mode 0 - t a(so) (2)(3) data output access time slave mode - 3x t master t dis(so) (2)(4) data output disable time slave mode 30 - t v(so) (2) data output valid time slave mode (after enable edge) - 60 t v(mo) (2) data output valid time master mode (after enable edge) -20 t h(so) (2) data output hold time slave mode (after enable edge) 15 - t h(mo) (2) master mode (after enable edge) 1- 1. parameters are given by selecting 10 ? mhz i/o output frequency. 2. values based on design simulation and/or charac terization results, and not tested in production. 3. min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in hi ? z. docid022344 rev 4 63/79 stm8tl5xxx electrical parameters 68 figure 28. spi timing diagram - slave mode and cpha = 0 figure 29. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd. a i 3 # + ) n p u t # 0 ( ! - / 3 ) ) . 0 5 4 - ) 3 / / 5 4 0 5 4 # 0 ( ! - 3 " / 5 4 - 3 " ) . " ) 4 / 5 4 , 3 " ) . , 3 " / 5 4 # 0 / , # 0 / , " ) 4 ) . . 3 3 i n p u t t 3 5 . 3 3 t c 3 # + t h . 3 3 t a 3 / t w 3 # , ( t w 3 # , , t v 3 / t h 3 / t r 3 # , t f 3 # , t d i s 3 / t s u 3 ) t h 3 ) a i 3 # + ) n p u t # 0 ( ! - / 3 ) ) . 0 5 4 - ) 3 / / 5 4 0 5 4 # 0 ( ! - 3 " / 5 4 - 3 " ) . " ) 4 / 5 4 , 3 " ) . , 3 " / 5 4 # 0 / , # 0 / , " ) 4 ) . t 3 5 . 3 3 t c 3 # + t h . 3 3 t a 3 / t w 3 # , ( t w 3 # , , t v 3 / t h 3 / t r 3 # , t f 3 # , t d i s 3 / t s u 3 ) t h 3 ) . 3 3 i n p u t electrical parameters stm8tl5xxx 64/79 docid022344 rev 4 figure 30. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd. a i 3 # + ) n p u t # 0 ( ! - / 3 ) / 5 4 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # , ( t w 3 # , , t r 3 # , t f 3 # , t h - ) ( i g h 3 # + ) n p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / docid022344 rev 4 65/79 stm8tl5xxx electrical parameters 68 inter ic control interface (i2c) subject to general operating conditions for v dd , f master , and t a unless otherwise specified. the stm8tl5xxx i2c interface meets the requirements of the standard i 2 c communication protocol described in the following table with the restrictions mentioned below. refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (sda and scl). note: for speeds around 200 khz, achieved speed can have 5% tolerance. for other speed ranges, achieved speed can have 2% tolerance. the above variations depend on the accuracy of the external components used. table 33. i 2 c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f sck must be at least 8 mhz to achieve max fast i 2 c speed (400 khz). unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has onl y to be met if the interface does not stretch the low period of scl signal. -0 (4) 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl ). 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf electrical parameters stm8tl5xxx 66/79 docid022344 rev 4 figure 31. typical application with i 2 c bus and timing diagram 1) 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd. 9.3.10 emc characteristics susceptibility tests are perfor med on a sample 36 basis duri ng product characterization. functional ems (electromagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). ? esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. th is test conforms with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(scl) t r(scl) t w(scll) t w(sclh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k sda stm8tl5xxx scl v dd 100 100 v dd 4.7k i 2 cbus docid022344 rev 4 67/79 stm8tl5xxx electrical parameters 68 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of em ission. this emission te st is in line with the norm sae j 1752/3 which sp ecifies the board and th e loading of each pin. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, refer to application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and charge device model. this test conforms to the jesd22-a114a/a115a standard. table 34. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance ufqfpn48, v dd = 3.3 v 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance ufqfpn48, v dd = 3.3 v, f hsi 3b table 35. emi data (1) 1. not tested in production. symbol parameter conditions monitored frequency band max vs. 16 mhz unit s emi peak level v dd = 3.6 v, t a = +25 c 0.1 mhz to 30 mhz -5 db v 30 mhz to 130 mhz -5 130 mhz to 1 ghz 0 sae emi level 1 - table 36. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 (2) 2. device sustained up to 3000 v during esd trials. v v esd(cdm) electrostatic discharge voltage (charge device model) 1000 electrical parameters stm8tl5xxx 68/79 docid022344 rev 4 static latch-up ? lu : 3 complementary static tests are required on 6 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to application note an1181. 9.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 14: general operating conditions on page 43 . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ? p intmax is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. ? p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd ? v oh) *i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 37. electrical sensitivities symbol parameter class lu static latch-up class ii table 38. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient ufqfpn 48 - 7 x 7 mm 32 c/w thermal resistance junction-ambient ufqfpn 28 - 4 x 4 mm 80 thermal resistance junction-ambient tssop20 110 docid022344 rev 4 69/79 stm8tl5xxx package characteristics 75 10 package characteristics 10.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their le vel of environmental compliance. ecopack? specifications, grade definitions and produc t status are available at: www.st.com. eco- pack? is an st trademark. 10.2 package mechanical data figure 32. ufqfpn48 - 48-lead ultra thin fine pitch quad flat no-lead package outline (7x7) 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. a0b9_me_v 3 d pin 1 indentifier l as er m a rking a re a ee d y d2 e2 expo s ed p a d a re a z 1 4 8 det a il z r 0.125 typ. 1 4 8 l c 0.500x45 pin1 corner a s e a ting pl a ne a1 b e ddd det a il y t package characteristics stm8tl5xxx 70/79 docid022344 rev 4 figure 33. ufqfpn48 recommended footprint 1. dimensions are in millimeters 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. table 39. ufqfpn48 - 48-lead ultra thin fi ne pitch quad flat no-lead package (7x7), package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min. typ. max. min. typ. max. a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 e2 5.400 5.500 5.600 0.2126 0.2165 0.2205 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 t 0.152 0.0060 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e 0.500 0.0197 ddd 0.080 0.0031 ! " ? - % ? & 0 docid022344 rev 4 71/79 stm8tl5xxx package characteristics 75 figure 34. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4x4) 1. drawing is not to scale. 2. dimensions are in millimeters. 3. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. table 40. ufqfpn28 - 28-lead ultra thin fi ne pitch quad flat no-lead package (4x4), package mechanical data dim. mm inches min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 -0.050 0.000 0.050 -0.0020 0.0000 0.0020 d 3.900 4.000 4.100 0.1535 0.1575 0.1614 d1 2.900 3.000 3.100 0.1142 0.1181 0.1220 e 3.900 4.000 4.100 0.1535 0.1575 0.1614 e1 2.900 3.000 3.100 0.1142 0.1181 0.1220 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 l1 0.250 0.350 0.450 0.0098 0.0138 0.0177 t 0.152 0.0060 4 e b 3 e a t i n g 0 l a n e ! ! # o x ? 0 i n c o r n e r , , 2 o 4 y p $ e t a i l : $ $ % % 0 i n ) $ 3 e a t i n g 0 l a n e " ! $ e t a i l : ! " ? - % ? 6 package characteristics stm8tl5xxx 72/79 docid022344 rev 4 figure 35. ufqfpn28 recommended footprint 1. dimensions are in millimeters 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e 0.500 0.0197 table 40. ufqfpn28 - 28-lead ultra thin fi ne pitch quad flat no-lead package (4x4), package mechanical data dim. mm inches min typ max min typ max ! " ? - % ? & 0 docid022344 rev 4 73/79 stm8tl5xxx package characteristics 75 figure 36. tssop20 - 20-pin thin shrink small outline package table 41. tssop20 - 20-pin thin shrink small outline package mechanical data dim. mm inches min typ max min typ max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 d 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 e 0.650 0.0256 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 8.0 0.0 8.0 aaa 0.100 0.0039 9 ! ? - % # 0 c , % % $ ! ! k e b ! , a a a package characteristics stm8tl5xxx 74/79 docid022344 rev 4 figure 37. tssop20 recommended footprint 1. dimensions are in millimeters. docid022344 rev 4 75/79 stm8tl5xxx device ordering information 75 11 device ordering information figure 38. stm8tl5xxx ordering information scheme 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. stm8 t l 5 3 g 4 u 6 tr pin count c = 48 pins g = 28 pins f = 20 pins package type u = ufqfpn p = tssop example: device family l = low power product type t = touch sensing temperature range 6 = -40 c to +85 c device type stm8 microcontroller family program memory size 4 = 16 kbytes shipping tr = tape & reel blank = tray sub-family type 5 = projective capacitive sub-family peripheral set 2 = light 3 = basic stm8 development tools stm8tl5xxx 76/79 docid022344 rev 4 12 stm8 development tools development tools for the stm8 microcontrollers include the very low-cost debugger and programmer tool st-link supported by a complete software tool package including c compiler, assembler and integrated development environment with high-level language debugger. in addition, the stm8 is to be supp orted by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st vis ual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8. a free ve rsion that outputs up to 32 kbytes of code is available. 12.1.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com. this package includes: st visual develop (stvd) ? full-featured integrated development environment from st, featuring ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface st visual programmer (stvp) ? easy-to-use, unlimited graphical interface allowing read, write and verify of your stm8 microcontro ller?s flash program memory, data eeprom and option bytes. stvp also offers project mo de for saving programming configurations and automating programming sequences. docid022344 rev 4 77/79 stm8tl5xxx stm8 development tools 77 12.1.2 stm-studio stm-studio helps debug and diagnose stm8 and stm32 applications while they are running by reading and displaying their vari ables in real-time. stm-studio perfectly complements traditional debugging tools to fi ne tune applications. it is well suited for debugging applications which cannot be stop ped, such as touchsensing applications. its easy-to-use, graphical interface features: ? non-intrusive read on-the-fly variables from ram while the application is running ? parse dwarf debugging information in the elf application executable file ? possibility to log data into a file, and replay later (exhausti ve record display, not real- time) ? 2 types of viewers: ? variable viewer: real-time wave forms, oscilloscope-like graphs ? touchpoint viewer: association of 2 variabl es, one on the x axis, one on the y axis 12.1.3 c and assembly toolchains control of c and assembly toolchains is seam lessly integrat ed into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: ? cosmic c comp iler for stm8 ? one free version that outputs up to 32 kbytes of code is available. for more informat ion, see www.cosmic-software.com. ? iar embedded workbench ? the c compiler for stm8 which is included in the toolset is free for up to 8kbytes of code. for more information, see www.iar.com. ? raisonance c compiler for stm8 ? one free version that outputs up to 32 kbytes of code. for more information, see www.raisonance.com. ? stm8 assembler linker ? free assembly toolchain included in the stvd toolset, which allows you to assemble and link your applicat ion source code. 12.2 programming tools during the development cycle, st -link provides in-circuit pr ogramming of the stm8 flash microcontroller on your application board via the swim protocol. for production environments, programmers will include a comp lete range of gang and automated programming solutions from thir d-party tool developers already supplying programmers for the stm8 family. revision history stm8tl5xxx 78/79 docid022344 rev 4 13 revision history table 42. document revision history date revision changes 14-oct-2011 1 initial release 04-apr-2012 2 added stm8tl52g4, STM8TL52F4, stm8tl53f4 part numbers added figure 15 , figure 17 , figure 18 , figure 19 , figure 20 , figure 21 , figure 22 , figure 23 , figure 24 , figure 25 , figure 26 , figure 27 updated figure 32 and table 39 added tssop20 package 06-aug-2013 3 removed ?stice? references and edited the text in section 3.2: development tools and section 12: stm8 development tools . in table 5: general hardware register map : ? changed the reset status from ?0x00? to ?0x01? on ? clk_pckenr2? row, ? split address block ?0x00 5055 to 0x00 509f? into ?0x00 5055 to 0x00 509d? with ?reserved, ? 0x00 509e? with ?syscfg? and ? 0x00 509f? with ?reserved?, ? added a footnote to rst_sr reset status value, ? updated clk_ccor reset status value to ?0x10?. updated description of opt0 in table 9: option byte description . updated v in max values in table 11: voltage characteristics . added section 9.3.4: proxsense regulator voltage . removed acc hsi_pxs rows from table 23: hsi_pxs oscillator characteristics and removed former figure 17 typical hsi_pxs frequency vs. vdd . added t prog and i prog max. values to table 26: flash program memory . removed v ol row with conditions i io =+20 ma and v dd =3.0 v from table 29: i/o static characteristics . updated ?proxsense i/o? conditions and min. values in ta ble 30 : output driving current (high sink ports) . added section 3.13: general purpose and basic timers . 07-aug-2013 4 updated opt0 default value in table 8: option bytes . docid022344 rev 4 79/79 stm8tl5xxx 79 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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